Last modified July 1, Alireza Khalafi is in charge of this page, akhalafi ece. Zain Navabi, navabi ece. Using this language for design, description and synthesis of hardware is emphasized.
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Contact Book Chapter 1. Karimi and Z. Journal Articles 1. Karimi , A. Kanuparthi, X. Wang, O. Sinanoglu, and R. Kannan, N. Karimi , R. Karri, and O. Karimi , O. DeTrano, N. Karri, X. Guo, C. Carlet, and S.
Guilley, "Exploiting small leakages in masks to turn a second-order attack into a first-order attack and improved rotating substitution box masking with linear code cosets," The Scientific World Journal, vol. Karimi and K. Karimi , M. Maniatakos, C.
Tirumurti, and Y. Maniatakos, A. Jas, C. Maniatakos, N. Karimi , C. Tirumurti, A. Jas, and Y. Alaghi, M. Sedghi, and Z. Conference Papers 1. Karimi , J. Danger, F. Guo, N. Karimi , F. Regazzoni, C.
Jin, and R. Hardware-Oriented Security and Trust Symp. HOST , , pp. DeTrano, S. Guilley, X. Karimi , and O. Sinanoglu, "Secure memristor-based main memory," Proc. Design Automation Conf. DAC , , pp. Sinanoglu, "Detection, diagnosis, and repair of faults in memristor-based memories," Proc. VTS , , pp. Sinanoglu, N.
Rajendran, R. Karri, Y. Jin, K. Huang, and Y. Makris, "Reconciling the IC test and security dichotomy," Proc. European Test Symp.
ETS , , pp. Karimi , K. Chakrabarty, P. Gupta, and S. Patil, "Test generation for clock domain crossing faults in integrated circuits," Proc. DATE , , pp. Karimi , Z. Kong, K. Patil, "Testing of clock-domain crossing faults in multi-core system-on-chip," Proc.
Asian Test Symp. ATS , , pp. Karimi , S. Sadeghi, and Z. Navabi, "Network-on-chip concurrent error recovery using functional switch faults," Proc. Makris, "Impact analysis of performance faults in modern microprocessors," Proc.
Makris, "Instruction-level impact comparison of RT- vs. Maniatakos, Y. Makris, and A. Jas, "On the correlation between controller faults and instruction-level errors in modern microprocessors," Proc. Test Conf. ITC , , pp. Sedghi, N. Karimi , and Z. Navabi, "NoC reconfiguration for utilizing the largest fault-free connected sub-structure," Proc.
Karimi , Y. Makris, A. Jas, and C. Tirumurti, "Design and evaluation of a timestamp-based concurrent error detection method CED in a modern microprocessor controller," Proc. Fathy, and Z. Navabi, "Reliable NoC architecture utilizing a robust rerouting algorithm," Proc. EWDTS , , pp.
Aminzadeh, S. Safari, and Z. Online Test Symp. IOLTS , , pp. Alaghi, N. Navabi, "Online NoC switch fault detection and diagnosis using a high level fault model," Proc. Mirkhani, Z. Navabi, and F. Navabi, "A dynamic reconfiguration method for error recovery of RT level designs," Proc.
East-West Design and Test Symp. Mirkhani, and Z. Karimi , P. Riahi, and Z. Navabi, "A survey of testability measurements at various abstraction levels," Proc. Riahi, Z. Navabi, N.
VHDL: Analysis and Modeling of Digital Systems
PROFESSOR NAVABI VHDL WORKS.
VHDL: Modular Design and Synthesis of Cores and Systems, 3rd Edition